Advanced Technology for Advanced Verification,Advanced Technology for Block Level
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Although constrained random stimulus generation is an automated way to achieve coverage of your design’s functionality during simulation, it is now possible to achieve even higher coverage, faster. Also, not all verification challenges are best addressed with the generic functional simulation approach. Some tasks require more application-specific capabilities, while others can benefit from static and/or formal analysis coupled with simulation. In this session, we will cover the use of graph-driven stimulus generation that will “straighten the curve” on your path to coverage closure, leading to orders of magnitude improvement in simulation productivity. We will also cover application-specific verification techniques for clock domain crossing verification and for verification of power management architectures for low power designs. Finally, we will show how formal verification can be used effectively, in both automatic and assertion-driven modes, to find bugs quickly and exhaustively verify correctness.
Duration: 42:40
Tags: Certe Testbench Studio, Questa Codelink, Questa® CDC Verification, Verification Management
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