Beat your functional verification/software development timescales with Acceleration/Emulation

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Multimedia

Off-line Debug of Multi-Core SoCs with Veloce Emulation

Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design...…View On-demand Web Seminar

Advanced UVM Debugging

This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar

The 2012 Wilson Research Group Functional Verification Study

Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.  In this presentation, Harry Foster...…View On-demand Web Seminar

Other Related Resources

Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation

White Paper: Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification...…View White Paper

Veloce System-Level Power Analysis and Verification

White Paper: Power analysis and verification need to move to the system level, improving upon and extending the capabilities and scope of RTL and gate-level techniques. The performance, capacity, and flexibility of...…View White Paper

Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation

White Paper: Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification...…View White Paper