Clock Domain Crossing Verification
Technology Overview
Abstract
Most ASIC and FPGA designs on the drawing board today have multiple asynchronous clocks. With traditional simulation and static timing based methodologies coming up short in verifying the interaction between asynchronous clock domains, designers are looking for clock-domain crossing (CDC) verification solutions that address all CDC issues. This session teaches you about the types of problems associated with clock-domain crossings, the things you can do to avoid these issues, and the application of an automated verification solution that ensures your design is free of CDC problems.
Duration: 15:17
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