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David Abercrombie at DAC 2012

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Why IC Designers Need New Double Patterning Debug Capabilities at 20nm

Jean-Marie Brunet, Director of DFM Product Marketing, discusses Mentor's history of collaboration with TSMC and highlights their work on design enabling support for 20nm.…View Technology Overview

Michael Buehler at DAC 2012

Interview with Mentor Graphics' Michael Buehler at DAC 2012.…View Technology Overview

Walden Rhines at DAC 2012

Interview with Mentor Graphics CEO Walden Rhines at DAC 2012.…View Technology Overview

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Double Patterning from Design Enablement to Verification

White Paper: Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges...…View White Paper

Self-aligned double-patterning (SADP) friendly detailed routing

White Paper: Among the possible double patterning strategies, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while lithoetch-litho-etc (LELE)...…View White Paper

Calibre Pattern Matching: Picture It, Match It...Done!

White Paper: Calibre Pattern Matching is an extension to SVRF that simplifies complex rule checks required for advanced IC processes. This white paper discusses the conditions that have created the need for pattern...…View White Paper

 
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