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Delivering 10X Design Improvements

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Low Pin Count Test with Embedded Compression

On-demand Web Seminar: This event will describe several methodologies that enable designers to reduce the number of pins and top level routing required for the application of high quality test. The focus will be on manufacturing...…View On-demand Web Seminar

Power-Aware Silicon Test: Understanding Testing and Power-Sensitive Designs

On-demand Web Seminar: During this presentation we discuss the trends, drivers and solutions for power-aware test that have emerged. We will take a look at the technologies where power-aware test required, how designers are looking...…View On-demand Web Seminar

Power Efficient Design Challenges and Trends

On-demand Web Seminar: This presentation covers key aspects to the forces from a technology and market perspective that are driving designers towards better energy efficient designs.…View On-demand Web Seminar

Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost

White Paper: The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand...…View White Paper

Memory Test and Repair Solution for ARM Processor Cores

White Paper: Many large systems-on-chip (SOC) designs today incorporate several third-party IP cores that cover a wide range of functionality. These cores often consist of high-performance embedded processors such as...…View White Paper

Defects and Defect Detection Industry Trends

White Paper: This white paper describes the known common manufacturing defects and methods for detecting defects.…View White Paper

 
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