Effective SoC Verification: The Hardware and Software Challenge
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How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized functional blocks stitched together with multiple power and clock domains. Using an example SoC design, this session will show how verification management, the embedded CPU, re-use of block-level verification IP, software, and acceleration combine to give you confidence that your SoC works and verification is complete.
Duration: 25:50
Tags: Certe Testbench Studio, Questa Codelink, Questa® CDC Verification, Verification Management
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