Effective SoC Verification: The Hardware and Software Challenge
How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized functional blocks stitched together with multiple power and clock domains. Using an example SoC design, this session will show how verification management, the embedded CPU, re-use of block-level verification IP, software, and acceleration combine to give you confidence that your SoC works and verification is complete.
Although constrained random stimulus generation is an automated way to achieve coverage of your design’s functionality during simulation, it is now possible to achieve even higher coverage, faster....…View Technology Overview
This video provides an overview of Mentor Graphic's ModelSim software. You will learn the essential skills needed to create a simulation environment and what tools are available to quickly debug the...…View On-demand Web Seminar
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