Functional Verification - Volume To Velocity - Tech Design Forum
Keynote Tech Design Forum Israel 2011: "From Volume to Velocity", presented by Stephen Bailey, Director of Marketing at Mentor Graphics.
There has been a remarkable acceleration in the adoption of advanced verification methodologies, languages and new standards. This is true across all types of IC design and geographic regions. Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density. They are looking beyond simply increasing the volume of verification to instead using advanced techniques to improve the velocity of verification.
The result is design teams have not lost ground on meeting schedule goals or first-pass silicon success even as design complexity has grown. Now the focus is shifting to appreciably improving those metrics while shrinking verification costs. Stephen Bailey, Director of Marketing at Mentor Graphics, will discuss the state of verification past, present and future. After examining the results from a leading verification survey, he'll look at how advanced techniques are taking hold in mainstream design.
About the Presenter
Stephen Bailey is the Director of Marketing for the Design Verification Technology division at Mentor Graphics. He has been part of the EDA industry for over 20 years, and his career has provided the opportunity to experience virtually every facet of electronic design. Mr. Bailey has served in several industry standards activities including VHDL IEEE 1076 working group chair, Property Specification Language (PSL) IEEE 1850 working group member, IEEE Design Automation Standards Committee secretary, Accellera Unified Power Format Technical Subcommittee chair, and Accellera Unified Coverage Interoperability Standard Technical Subcommittee member.
UVM Sequences in Depth
In this webinar, we will walk through the mechanics of setting up and executing Slave Sequences in a responder. We will also walk through modeling an interrupt sequence and show how to have interrupt...…
Other Related Resources
Hardware Emulation Tackles SoC Memory Systems
White Paper: How does Veloce’s expanded support for SoC memory designs stack up against old school FPGA prototyping? Find out in this article comparing them. You might be surprised at what emulators with memory...…
When to Use Simulation, When to Use Emulation
White Paper: Should you emulate or simulate? In this brief historical review, Dr. Lauro Rizzatti compares the two and reveals when to use which and explains why only emulation can verify embedded SW in an SoC design.…
Software Debug Using Lauterbach TRACE32 on Veloce with Physical and Virtual Probes
White Paper: This whitepaper discusses how the Lauterbach tools and Veloce emulator can work in both virtual and physical environments to give a consistent view for software debug. By connecting to either the virtual...…