How do you determine the right way to improve your verification capability?
Whatever you are designing, verification is becoming an increasingly complex and time consuming activity. Determining how best to improve your verification capability can seem almost as difficult doing the verification itself. This presentation will outline an assessment process, based on a verification capability model, used to understand the most effective way of improving your current verification approach. The presentation will be illustrated with some case studies where customers using this process have been able to significantly improve their verification capabilities.
Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…
The 2012 Wilson Research Group Functional Verification Study
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...…
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SystemVerilog for Verification: Foundation
Training Course: The SystemVerilog for Verification: Foundation course is designed to introduce verification engineers to the SystemVerilog language. The course describes the enhancements that have been made to Verilog,...…
STMicroelectronics: Simulation + Emulation = Verification Success
Success Story: Developing an ARM-based reference design, STMicroelectronics engineers linked a testbench running on a simulator with a design executed on an emulator, taking advantage of the best of both verification...…