How do you determine the right way to improve your verification capability?
Whatever you are designing, verification is becoming an increasingly complex and time consuming activity. Determining how best to improve your verification capability can seem almost as difficult doing the verification itself. This presentation will outline an assessment process, based on a verification capability model, used to understand the most effective way of improving your current verification approach. The presentation will be illustrated with some case studies where customers using this process have been able to significantly improve their verification capabilities.
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...…View On-demand Web Seminar
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FPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions
White Paper: This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting...…View White Paper
Success Story: How Dot Hill designed an verified a new 30-million-gate RAID accelerator using advanced OVM-based verification.…View Success Story