Improving Visibility & Efficiency with Verification Management
Verification management is one of the most important factors in today’s verification of silicon chips and SoC designs. Every development team manages their verification process in some way, but how easy it is to answer certain questions reveals the effectiveness and completeness of each approach in delivering on schedule. Where are we in the verification process? Are we ready to sign-off? If a change is made to a design block, which tests need to be re-run to get the best coverage? What affect on the verification process does a last minute change to my functional specification have? The fact that all of these questions are not easily answered by the vast majority of verification plans demonstrates the need for the automated storage and analysis of verification data within the verification process.
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...…View On-demand Web Seminar
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