Make Functional Verification your Competitive Differentiator
Companies that master the functional verification challenges for today's chips have a competitive advantage in that they can get products to market faster. In this keynote we identify the core pieces of technology and methodology that not only maximize design quality, but also ensure maximum verification productivity. We will further show how Mentors scalable verification platform is uniquely positioned to deliver this next generation of verification productivity.
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...…View On-demand Web Seminar
Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design...…View On-demand Web Seminar
Other Related Resources
Success Story: How Dot Hill designed an verified a new 30-million-gate RAID accelerator using advanced OVM-based verification.…View Success Story
White Paper: With power becoming a critical design constraint in the design environment, designers are utilizing advanced techniques to minimize power consumption in their designs. As a result, the RTL design is being...…View White Paper