Overview of Calibre PERC
Technology Overview
Abstract
Calibre PERC is a reliability verification platform, providing robust, full chip, sign-off quality checks in an integrated environment. From your first schematic, through SoC assembly, to the final layout, we are able to provide a repeatable, efficient and effective reliability verification platform capable of verifying your most challenging reliability issues.
Duration: 10:02
Related Resources
Multimedia
Foundry Solutions Video Blog: TSMC OIP Conference
At TSMC's Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described...…View Technology Overview
Beyond Physical Verification: Advanced Electrical Rule Checking on Layout
As designs incorporate more mixed-signal content, the complexity of checks for issues such as Electrostatic Discharge has increased, and reliance on manual checking and time-consuming simulation becomes...…View On-demand Web Seminar
Robust Verification of Low Power Designs
The increased use of thin-oxide transistors, which are less robust to electrical failure in mixed-signal and multi-voltage designs, have ushered in a new era of verification challenges. Correct connection...…View On-demand Web Seminar
Other Related Resources
An Innovative Approach to High Frequency Analysis of IC Layouts
White Paper: Traditional high frequency analysis (HFA) of integrated circuit designs is based on an empirical approach, which is slow and cumbersome. It is costly to develop the initial model for an IC process, and...…View White Paper
Solving Electrostatic Discharge Design Issues with Calibre® PERC™
White Paper: With the progress of technology nodes, circuit designers are now encountering challenging circuit reliability issues that have no simple solutions. Calibre PERC delivers fast, comprehensive and accurate...…View White Paper
Describing PERC-based Intent Driven Design
White Paper: In this paper, we present a fully automated CAD solution that captures the designer’s intent from the schematic netlist, and links these annotations to the proper devices or nets on the physical layout...…View White Paper