OVM: The Open Verification Methodology
This session covers the use and benefits of the Open Verification Methodology (OVM). The OVM brings together verification knowledge, experience and expertise to provide an approach to building verification IP and testbenches powerful enough to meet the most demanding requirements, yet easy to adopt. This session illustrates all aspects of the OVM, including the following: planning for verification, testbench architecture, transaction-level modeling in verification, sequential stimulus and coverage, and block-to-system-level reuse.
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...…View On-demand Web Seminar
Other Related Resources
FPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions
White Paper: This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting...…View White Paper
Success Story: How Dot Hill designed an verified a new 30-million-gate RAID accelerator using advanced OVM-based verification.…View Success Story