Processor Driven Verification
Using a full-functional processor model to drive bus-cycles into a block or chip level simulation is a powerful method to verify SoC designs. Since the end product is processor driven, this “real world” approach to verification is superior to bus-functional models. This session will present the full range of processor driven methods from sign-off simulation using an RTL pin-level model to OVM transaction-level processor models. Included is a live demonstration of Questa Codelink, a tightly integrated source-level debugger for processor-driven tests.
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...…View On-demand Web Seminar
Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design...…View On-demand Web Seminar
Other Related Resources
Success Story: How Dot Hill designed an verified a new 30-million-gate RAID accelerator using advanced OVM-based verification.…View Success Story
White Paper: With power becoming a critical design constraint in the design environment, designers are utilizing advanced techniques to minimize power consumption in their designs. As a result, the RTL design is being...…View White Paper