Questa: SystemVerilog Verification from Requirements to Coverage Closure
Technology Overview
Abstract
SystemVerilog delivers advanced functional verification techniques in an industry standard language. However, the effective, predictable verification of electronic systems takes much more than constrained-random stimulus generation and a few covergroups and assertions. It starts with a verification plan derived from the system’s functional requirements and tracked through appropriate measures of verification completeness, efficiency and effectiveness. Mentor Graphics will present proven SystemVerilog verification solutions that effectively manage the verification process with leading technology that delivers coverage closure.
Duration: 35:54
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