Re-defining Verification Performance
Performance is key to achieving verification productivity. Yet, traditional brute force approaches to improving performance will only provide incremental benefits, which will not keep up with Moore's Law. Achieving 100x to 1000x improvements in verification performance requires thinking outside the box. This keynote provides a historical survey of ways other industries have faced their performance issues, drawing on examples ranging from Henry Ford to the Intel 8088 microprocessor. Then, based on these observations from other industries, a prescription is offered to address today's verification performance issues.
This webinar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow and show you how Questa employs intelligent automation...…View On-demand Web Seminar
What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way...…View On-demand Web Seminar
This webinar provides an introduction to the use of code coverage in today’s HDL design and verification flows.…View On-demand Web Seminar
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Success Story: Developing an ARM-based reference design, STMicroelectronics engineers linked a testbench running on a simulator with a design executed on an emulator, taking advantage of the best of both verification...…View Success Story