Simulating the Gate-Level Netlist with Timing

Technology Overview

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Gate-level simulation verifies the output of the synthesis and place & route tools and incorporates timing to bring the model closer to real implementation. It ensures that a device will perform precisely to its DO-254 requirements. In this video, DO-254 program manager Michelle Lange demonstrates how Mentor Graphics ModelSim can help with gate-level simulation.

Duration: 14:11

Tags: ModelSim®

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