Using Logical Equivalency Checking to Verify the Netllist
A logic equivalency checking (LEC) verification process supports DO-254 compliance and helps reduce dependence on gate-level simulation for complex FPGA projects. In this video, DO-254 program manager Michelle Lange explains the LEC process in the DO-254 lifecycle, and how Mentor Graphics FormalPro can save time and ensure accuracy.
In this session, Jim Henson, Product Marketing Manager at Mentor Graphics discusses IEC 61508, "Functional safety of electrical/electronic/programmable electronic safety-related systems." This...…View Technology Overview
Improving productivity has many forms, simulation performance, debug effectiveness, even writing test scenarios. We will highlight high value techniques for improving throughput.…View On-demand Web Seminar
What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way...…View On-demand Web Seminar
Other Related Resources
White Paper: Formal verification offers a solution that is quick, exhaustive and allows for efficient debug. It’s true that traditionally, chip-level formal verification is impractical. The approach usually targets...…View White Paper
White Paper: DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based...…View White Paper