Verification Planning and Management Consulting
Author and Senior Mentor Consultant Peet James presents a sample of our solution in this Verification Planning & Management Module. Mr. James explains how to transform the typically open-ended verification process into a predictable and repeatable endeavor.
The gap between your ability to design and your ability to verify is growing fast. Mentor Consulting minimizes the design/verification gap through industry-proven techniques and tools to improve the quality, efficiency and determinism of your verification project.
UVM Sequences in Depth
In this webinar, we will walk through the mechanics of setting up and executing Slave Sequences in a responder. We will also walk through modeling an interrupt sequence and show how to have interrupt...…
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White Paper: How does Veloce’s expanded support for SoC memory designs stack up against old school FPGA prototyping? Find out in this article comparing them. You might be surprised at what emulators with memory...…
When to Use Simulation, When to Use Emulation
White Paper: Should you emulate or simulate? In this brief historical review, Dr. Lauro Rizzatti compares the two and reveals when to use which and explains why only emulation can verify embedded SW in an SoC design.…
Software Debug Using Lauterbach TRACE32 on Veloce with Physical and Virtual Probes
White Paper: This whitepaper discusses how the Lauterbach tools and Veloce emulator can work in both virtual and physical environments to give a consistent view for software debug. By connecting to either the virtual...…