Verification Planning and Management Consulting
Author and Senior Mentor Consultant Peet James presents a sample of our solution in this Verification Planning & Management Module. Mr. James explains how to transform the typically open-ended verification process into a predictable and repeatable endeavor.
The gap between your ability to design and your ability to verify is growing fast. Mentor Consulting minimizes the design/verification gap through industry-proven techniques and tools to improve the quality, efficiency and determinism of your verification project.
UVM Sequences in Depth
In this webinar, we will walk through the mechanics of setting up and executing Slave Sequences in a responder. We will also walk through modeling an interrupt sequence and show how to have interrupt...…
Veloce Speeds Debug of Ostendo Mobile 3D Projector on Chip
Phuong-Anh, Sr. ASIC Verification Engineer at Ostendo Technologies Inc. describes how the Veloce emulator’s ability to run extensive, long tests allowed them to run many iterations of their firmware...…
Other Related Resources
UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment
Journal Article: Developing UVM-based testbenches from scratch is a time consuming and error-prone process. Engineers have to learn object oriented programming (OOP), a technique with which ASIC developers generally are...…
Increasing Verification Productivity Through Functional Coverage Management Automation
Journal Article: Functional coverage plays a very important role in verifying the completeness of a design. However customizing a coverage plan for different chips, users, specification versions, etc. is a very tedious...…