Why is OVM and Hardware Acceleration Such a Viable Solution
On-demand Web Seminar
Abstract
OVM promotes the use of untimed transaction-based testbenches for simulation and such an approach can be complimentary with hardware acceleration for both high performance and effective creation of system testbenches. This Tuesday Tech Talk will explain a simple solution to address the challenge of employing hardware acceleration in conjunction with transaction-based testbenches. A real example, together with the benchmark data showing the performance advantages, will be discussed.
Duration: 25:56
Opens in New Window/External URL
Tags
Details
Overview
This webinar will explain a simple solution to address the challenge of employing hardware acceleration in conjunction with transaction-based testbenches.
A real example, together with the benchmark data showing the performance advantages, will be discussed. OVM promotes the use of untimed transaction-based testbenches for simulation and such an approach can be complimentary with hardware acceleration for both high performance and effective creation of system testbenches.
What You Will Learn
- The advantages of an OVM transaction-based testbench
- The advantages of hardware acceleration for verification
- How to combine these two techniques effectively
About the Presenter
Jim Kenney
Jim Kenney has 30 years of simulation experience including hardware emulation and HW/SW co-simulation. He’s worked as a developer, applications engineer, and is currently the Marketing Director for Mentor’s Emulation Division. He holds a BSEE from Clemson University.
Who Should View
- Verification Manager
- Verification Engineers
- ASIC/SoC Design Managers
Related Resources
Multimedia
Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar
The 2012 Wilson Research Group Functional Verification Study
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...…View On-demand Web Seminar
Other Related Resources
FPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions
White Paper: This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting...…View White Paper
Dot Hill Systems Corp.
Success Story: How Dot Hill designed an verified a new 30-million-gate RAID accelerator using advanced OVM-based verification.…View Success Story
Parameters and OVM: Can’t They Just Get Along?
White Paper: This paper discusses the methods that have proven useful for verifying a highly parameterized DUT within an OVM testbench. This includes enhancing the default OVM functionality to create parameterized OVM...…View White Paper