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Why is OVM and Hardware Acceleration Such a Viable Solution

Details

Overview

This webinar will explain a simple solution to address the challenge of employing hardware acceleration in conjunction with transaction-based testbenches.

A real example, together with the benchmark data showing the performance advantages, will be discussed. OVM promotes the use of untimed transaction-based testbenches for simulation and such an approach can be complimentary with hardware acceleration for both high performance and effective creation of system testbenches.

What You Will Learn

  • The advantages of an OVM transaction-based testbench
  • The advantages of hardware acceleration for verification
  • How to combine these two techniques effectively

About the Presenter

Presenter Image Jim Kenney

Jim Kenney has 30 years of simulation experience including hardware emulation and HW/SW co-simulation. He’s worked as a developer, applications engineer, and is currently the Marketing Director for Mentor’s Emulation Division. He holds a BSEE from Clemson University.

Who Should View

  • Verification Manager
  • Verification Engineers
  • ASIC/SoC Design Managers
 
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