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Questa Formal's AutoCheck - The Push-Button Way to Find Bugs



This webinar will deliver an overview of the Autocheck feature of Questa Formal.

The Autocheck feature of the Questa Formal Verification tool from Mentor Graphics allows designers and verification engineers to quickly and easily verify that a design is free of many common functional design issues. This feature uses automatic assertion creation and formal sequential analysis to verify the design before a testbench is available and without user-written assertions.

Common design checks performed by Autocheck include FSM checks, deadcode/stuck checks, arithmetic checks, register and bus checks to name a few. Also included is a series of checks for X verification and initialization effects in your design. Autocheck can also automatically generate an exclusion file for improving simulation code coverage thus reducing the amount of time wasted trying to hit unreachable states.

What You Will Learn

  • How Questa AutoCheck can improve the quality of your design before running simulation
  • How you can verify the effect of X's and initialization issues in your design before taking it to h/w
  • How you can improve your code coverage results through the use of automatically generated exclusions
  • A brief overview of Questa AutoCheck using a simple example

About the Presenter

Presenter Image Mark Eslinger

Mr. Eslinger has over 20 years of experience in chip design & verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics Mr Eslinger has a special focus on assertion-based methods and formal verification. In this role he works with customers worldwide to help them adopting advanced methodologies. Prior to Mentor Mr. Eslinger has held positions in the engineering and technical marketing organizations in the semiconductor, systems and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. Mr Eslinger holds a MSEE from Santa Clara University.

Who Should View

  • Design Verification Engineers and Managers

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