Sign In
Forgot Password?
Sign In | | Create Account

Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models Webinar

Details

Overview

Multi-clock designs are subject to metastability causing mismatches between simulation and the silicon reality. This webinar focuses on how to ensure that simulations of such designs can nevertheless be accurate predictors of silicon behavior.

We show through a set of detailed examples how non-determinism caused by metastability in clock domain crossings can lead to functional problems. We discuss the pros and cons of some current approaches to model metastability, and explain how the comprehensive Questa CDC solution helps you find and eliminate these problems during the RTL simulation of your ASIC and FPGA designs.

What You Will Learn

  • How metastability can lead to functional issues in silicon
  • Why metastability cannot be verified by traditional simulation methods
  • The differences between current metastability modeling techniques
  • How Questa CDC can help to eliminate functional issues caused by metastability

 

About the Presenter

Presenter Image Kurt Takara

Mr. Takara has over 20 years of experience in engineering design and verification, technical marketing and engineering services. He is a Technical Marketing Engineer at Mentor Graphics Corporation and specializes in assertion-based verification methods and applications, including formal and clock-domain crossing (CDC) verification. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.

Who Should View

  • Design Verification Engineers and Managers

Related Resources

Multimedia

Advanced UVM Debugging

This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar

The 2012 Wilson Research Group Functional Verification Study

Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.  In this presentation, Harry Foster...…View On-demand Web Seminar

The Questa Platform: Generating Coverage Models and Achieving Coverage Closure - DAC 2012

Recent industry surveys show that two-thirds of new design projects fall behind schedule due to verification. In addition, 70% of these designs fail at least once after verification is completed. With over...…View Technology Overview

Other Related Resources

Understanding electronic IP: common issues and how to find them

White Paper: Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology...…View White Paper

Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools

White Paper: DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based...…View White Paper

Applied Micro Circuits Corporation (AMCC)

Success Story: Applied Micro Circuits Corporation (AMCC) adopts Questa CDC for their complex clock domain crossing verification.…View Success Story

 
Online Chat