Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models Webinar
On-demand Web Seminar
This webinar focuses on the how to ensure that simulations of such designs can nevertheless be accurate predictors of silicon behavior. We show through a set of detailed examples how non-determinism caused by metastability in clock domain crossings can lead to functional problems.
Multi-clock designs are subject to metastability causing mismatches between simulation and the silicon reality. This webinar focuses on how to ensure that simulations of such designs can nevertheless be accurate predictors of silicon behavior.
We show through a set of detailed examples how non-determinism caused by metastability in clock domain crossings can lead to functional problems. We discuss the pros and cons of some current approaches to model metastability, and explain how the comprehensive Questa CDC solution helps you find and eliminate these problems during the RTL simulation of your ASIC and FPGA designs.
What You Will Learn
- How metastability can lead to functional issues in silicon
- Why metastability cannot be verified by traditional simulation methods
- The differences between current metastability modeling techniques
- How Questa CDC can help to eliminate functional issues caused by metastability
About the Presenter
Mr. Takara has over 20 years of experience in engineering design and verification, technical marketing and engineering services. He is a Technical Marketing Engineer at Mentor Graphics Corporation and specializes in assertion-based verification methods and applications, including formal and clock-domain crossing (CDC) verification. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.
Who Should View
- Design Verification Engineers and Managers
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