Debug Productivity with Questa: Introduction to advanced debug features in Questa for SystemVerilog class-based TB, OVM/UVM, and hard to find problems in RTL
On-demand Web Seminar
This webinar will introduce the advanced debug capabilities available in Questa for class-based debug of OOP environments with SystemVerilog, OVM, UVM and SystemC, Assertion debug with SVA or PSL and advanced traditional RTL debug with process debug, waveform compare, transaction-level debug, source code tracing, schematic view, causality tracing, X-trace, and other productivity features.
No one argues that today’s designs are rapidly growing in both size and complexity. Often IP is brought together from multiple sources (both internal and external), and can involve multiple design languages. To increase productivity and quality, verification engineers are also adopting advanced techniques and methodologies such as ABV(Assertion Based Verification)and OVM/UVM (Open/Universal Verification Methodology) and using languages such as SystemC and SystemVerilog. This variation and complexity in the verification environment demands new automation and capabilities for effective debug.
With native support of VHDL, Verilog, SystemVerilog and SystemC, Questa has a rich set of debug technology and functionality to help diagnose problems and find bugs fast. This webinar will introduce the advanced debug capabilities available in Questa for class-based debug of OOP environments with SystemVerilog, OVM, UVM and SystemC, Assertion debug with SVA or PSL and advanced traditional RTL debug with process debug, waveform compare, transaction-level debug, source code tracing, schematic view, causality tracing, X-trace, and other productivity features.
What You Will Learn
An introduction to:
- How advanced debug capabilities can help you rapidly uncover design issues
- How Questa's assertion debug capabilities can help you understand and debug your assertions
- How Questa's advanced SystemVerilog debug capabilities can you help you debug your OOP code using familiar hardware debug techniques
About the Presenter
Ms. Burns has over 25 years of experience in the chip design and the EDA industries in various roles of engineering, applications engineering, technical marketing and product management. She is currently the Product Manager in the Design and Verification Technology Division at Mentor Graphics responsible for simulation with Questa and ModelSim. Prior to Mentor Graphics, Ms. Burns has held engineering and marketing positions at CoWare, Cadence, Synopsys, Viewlogic, Computervision and Intel. She holds a BSCpE from Oregon State University.
Who Should View
- Design and Verification Engineers
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