Raising Productivity Using Abstract UVM Stimulus and Intelligent Automation
On-demand Web Seminar
The benefits that UVM provides in specifying modular reusable testbenches have been well documented. Regardless of these benefits, however, the need to adequately model functional coverage, and efficiently create stimuli to reach your coverage goals, remains. The use of UVM sequences allows encapsulation of constrained-random stimulus that can be reused, and virtual sequences allow composition to orchestrate stimuli on multiple interfaces to your DUT. Unfortunately, the use of procedural constraint-based coding for stimulus has two distinct disadvantages. First, since constraints and coverage goals are distinct language features in SystemVerilog, they must be coded separately and there’s no easy way to map one to the other. Second, the reliance on constrained-random stimulus means that specific cases are likely to be repeated, leading to an asymptotic approach to your coverage goals.
Raising the level of stimulus abstraction allows you to specify your stimulus once and integrate the coverage model directly in the specification. This abstract stimulus can easily be mapped to UVM sequences at multiple levels of abstraction as well as to software for execution on a processor model, greatly enhancing the reusability of the stimulus. Intelligent Automation makes the execution of the stimuli more productive by reaching all coverage goals without the repetition inherent in constrained-random execution. The productivity advantages become even more pronounced as stimuli across multiple interfaces are composed into larger specifications.
This webinar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow and show you how Questa employs intelligent automation to achieve coverage closure faster.
What You Will Learn
- Mapping existing UVM sequences and transactions to abstract stimulus specifications
- Targeting coverage in your stimulus specification
- Creating abstract stimulus sequences for UVM
- Using Testbench Automation at the agent level
- Multi-interface Testbench Automation
- Mapping abstract stimulus to software to augment your testing
About the Presenter
Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.
Who Should View
- Verification Engineers and Managers
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