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Sequence Layering

Details

Overview

Many protocols have a hierarchical definition, and sometimes we may want to create a protocol-independent layer on top of a standard protocol to support the development of protocol-independent components and tests. This session will show how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.

What You Will Learn

  • How to model transactions for sequence layering
  • How to organize components to facilitate reuse in layering
  • How to develop a translator sequence and "reconstruction monitor" for each sequence layer
  • How to create and manage configuration of the layering components
     

About the Presenter

Presenter Image Tom Fitzpatrick

Verification Technologist

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Who Should View

  • Design and Verification Engineers and Managers

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