Power Aware Verification
On-demand Web Seminar
This seminar will present an example design with multiple power domains, power supply networks, and a power control unit. It will present methods used to define the power management architecture, to model power distribution, and to control the power states of the design in a way that that it can be successfully verified with dynamic simulation techniques.
Low power design requires partitioning of a chip into potentially many separate power domains that can be independently powered. For correct operation, on-chip active power management must orchestrate power state transitions as the various domains are powered up and down, and must mediate the interactions between domains in different power states. Power aware verification checks that the planned active power management architecture and controls will operate correctly and will enable the design to operate correctly as the design transitions from one power mode to another.
What You Will Learn
- What are the key components required in a system with active power management
- Some potential approaches for modelling and controlling a low power system
- What are the elements of verification that need to be considered to ensure a fully functioning low power system
About the Presenter
Mark has been involved in the design & verification of complex SoC’s for over 15 years with positions in a number of commercial and Mil-aero companies. He has worked in his current role, as an applications engineer with Mentor Graphics for the past 10 years. Mark holds a BEng in Digital Systems engineering from the University of the West of England, UK.
Who Should View
- Verification Engineers
- Design Engineers
UVM Sequences in Depth
In this webinar, we will walk through the mechanics of setting up and executing Slave Sequences in a responder. We will also walk through modeling an interrupt sequence and show how to have interrupt...…
Other Related Resources
Hardware Emulation Goes Mainstream
White Paper: Article in Insider reprinted from June 2014 by renowned Verification Consultant, Dr. Lauro Rizzatti. These days, you’d need to be buried under a pile of verification reports not to know that hardware...…
SystemVerilog Object Oriented Programming
Training Course: The SystemVerilog for Verification: Object Oriented Programming course is designed to introduce verification engineers to class based programming in SystemVerilog. Topics covered include dynamic processes,...…