Using Code Coverage with ModelSim
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With today's complex SoCs, the time spent on verification now consumes 70 percent of the total development time. A more efficient and effective verification methodology is crucial for improving first pass silicon success. Gathering and measuring coverage statistics are a critical part of this methodology. Coverage metrics are needed to assess the extent and quality of verification functionality, interface behaviors and corner cases for RTL structures. These metrics allow you to focus on actionable portions of the design. This session will discuss how to perform an easy measurement techniques with ModelSim that gets you well on your way toward 100% Coverage .
Duration: 60:00
Tags: ModelSim®
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Details
Overview
With today's complex SoCs, the time spent on verification now consumes 70 percent of the total development time. A more efficient and effective verification methodology is crucial for improving first pass silicon success. Gathering and measuring coverage statistics are a critical part of this methodology. Coverage metrics are needed to assess the extent and quality of verification functionality, interface behaviors and corner cases for RTL structures. These metrics allow you to focus on actionable portions of the design. This session will discuss how to perform an easy measurement techniques with ModelSim that gets you well on your way toward 100% Coverage.
What You Will Learn
- Coverage Options
- How to Analyze Coverage Data
- How to Save and Merge Coverage Data
About the Presenter
Walter Gude
Walter has 19 years experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various projects including time spent in Munich Germany and Helsinki Finland. For the last 5 years Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.
Who Should View
- Design and Verification engineers
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