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UVM Debug



UVM class-based testbenches have become as complex as the designs they are meant to verify, and are, in fact, large object-oriented software designs. As such, new debugging techniques and tools must be employed, beyond the usual RTL debugging techniques that designers have used for years. Through a combination of coding techniques (as documented in the DVCon 2012 2nd Place Best Paper, “Better Living Through Better Class-Based SystemVerilog Debug”) and the unique debug facilities in the Questa Verification Platform, this online webinar will show you how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.

What You Will Learn

  • Developing a Strategy for Debug
  • General SystemVerilog debug coding techniques
  • SystemVerilog Class-based Debug features in Questa
  • UVM-Specific Debug in Questa
  • Viewing your testbench structure
  • Transaction-based debug
  • UVM Debug utilities
  • Organizing files and using packages

About the Presenter

Presenter Image Tom Fitzpatrick

Verification Technologist

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Who Should View

  • Design and Verification Engineers and Managers

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