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UVM Sequences in Depth

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Overview

In UVM, sequences can provide a wealth of functionality beyond initiating stimulus on a particular interface. Often designs require the verification environment to respond to traffic from the DUT, and sequences can model this behavior as well. By modeling responders through the use of Slave Sequences, UVM enhances reuse by encapsulating the functionality in sequences that can be controlled from the test, without having to replace the agent connected to the DUT. In this webinar, we will walk through the mechanics of setting up and executing Slave Sequences in a responder. We will also walk through modeling an interrupt sequence and show how to have interrupt sequences running in conjunction with other stimulus sequences.

What You Will Learn

  • Review sequence API
  • How to use Slave Sequences to represent “responder” functionality
  • How to replace one Slave Sequence with another
  • Review Virtual Sequences to coordinate master/slave sequences
  • How to implement an interrupt sequence
 

Who Should Attend

  • Verification engineers and managers

About the Presenter

Presenter Image Tom Fitzpatrick

Verification Technologist

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

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