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Off-line Debug of Multi-Core SoCs with Veloce Emulation



Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design and verification. One obstacle to system level integration, is the difficulty in debugging early-stage embedded software interaction with multi-core design hardware. This presentation and demonstration will introduce a solution to reduce debug time and effort required to ensure that SoC firmware and device drivers interact seamlessly with design hardware. Veloce Codelink is an innovative off-line debugging solution with instant replay, that can double the effectiveness of Veloce Solo, Quattro, Grande, Maximus, and even Veloce2 emulation systems.

Who Should View

  • Design Verification Engineers and Managers

What You Will Learn

  • How to debug emulation runs off-line, freeing up emulators for running more regressions
  • How to use "instant replay" of long emulation runs, for joystick debugging
  • How to maintain multi-core synchronization of HW and SW emulation views
  • How to reduce time spent debugging emulation failures from days to minutes

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