Verification Strategy for Mixed-Signal SoCs
Requires Flash Player.
This Technical discussion will look into various tools available for Analog design verification, help understand underlying techniques and how they fit into SoC verification and how to take advantage of those tools. It will cover the various verification options available when putting mixed-signal blocks together in a SOC and the benefits and weakness of each.
Duration: 30:21
Tags: Analog Mixed-Signal, Questa ADMS
View On-demand Web Seminar (Opens in New Window/External URL)
Details
Overview
This webinar will look into various tools available for Analog design verification, help understand underlying techniques and how they fit into SoC verification and how to take advantage of those tools. It will cover the various verification options available when putting mixed-signal blocks together in a SOC and the benefits and weakness of each.
The designers have multiple choices of tools and methodologies to use for Mixed-Signal design verification.
Setting up the verification environment in early phase of design and choosing the right tools helps in efficient verification of design. The ever increasing design size and complexity of SoCs makes the choices non-trivial.
What You Will Learn
- The tradeoffs necessary to achieve adequate coverage in reasonable time in mixed-signal SoC verification
- The features and functions of a mixed-signal environment that are necessary for a flexible verification strategy
About the Presenter
Atul Pandey
Atul Pandey is a European Product Specialist for Analog and Mixed Signal solutions. He is supporting customers on Mentor's AMS products and solutions. He joined Mentor Graphics in 2008.Atul has expertise in Analog and Digital Circuit Design and Verification .Prior to joining Mentor Graphics, He has worked with STMicroelectronics, Intel and Infineon/Qimonda between 2001 and 2008 as Analog circuit designer on variety of Analog circuit blocks and IPs. Atul holds a Masters Degree in Integrated Electronics and Circuits from Indian Institute of Technology, Delhi(India).
Who Should View
- System engineers performing verification of mixed analog and digital systems
- Project leaders of mixed-signal designs concerned about design complexity and how to reduce risk with an appropriate verification strategy
- Analog design engineers who create IP for mixed signal ICs and digital design engineers who are seeing analog portions entering their designs
- CAD managers responsible for mixed-signal design and verification tools
Related Resources
Multimedia
More UVM Registers
The inclusion of the Register Layer was one of the most requested features of UVM. This session will expand on the introductory session delivered in October to discuss how to implement registers and also...…View On-demand Web Seminar
Verification Management and Planning
There are three dimensions to any IC design project: the process, the tools and the data. Mentor Graphics Questa® Verification Management offers a comprehensive approach to verification management that...…View On-demand Web Seminar
Other Related Resources
Using Assertions to Satisfy Elemental Analysis
White Paper: This paper discusses DO-254 and what it requires for verification (including advanced methods for DAL A/B designs), explains the original intent of Elemental Analysis, the way it is typically satisfied...…View White Paper
Virtual Devices for Protocol-Specific Host and Peripheral Interfaces
White Paper: This paper provides a brief genealogy of virtual devices, describes their characteristics and benefits, and presents two design applications that demonstrate its utility and effectiveness.…View White Paper
Understanding electronic IP: common issues and how to find them
White Paper: Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology...…View White Paper
