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Verifying Complex SoC Designs with Questa Codelink

Details

Overview

Verifying multiple blocks of design IP and achieving coverage closure is challenging enough. But verifying an entire SoC, with processors, memory, busses, and peripherals can be an enormous challenge, often involving a combination of simulation and emulation. This session shows how Questa Codelink helps verification engineers reduce the time spent finding design errors and debugging them, at the SoC level, in both simulation and emulation environments.

What You Will Learn

  • Non-invasive tracing and logging of simulation at the SoC level
  • A robust multi-window, multi-view debugging system that supports multi-processor designs
  • Acceleration of the processors to enable faster simulation
  • Virtual emulation for debugging that frees up expensive emulation capacity for more regressions.

About the Presenter

Presenter Image Mark Olen

Product Marketing Manager, Design Verification Technology

Mark Olen is the Testbench Automation Solutions Manager in the Design Verification Technology Division at Mentor Graphics. He has been at Mentor for over 10 years, and has over 25 years of experience in semiconductor design, verification, and test industries. Mark graduated from the Massachusetts Institute of Technology.

Who Should View

  • Design Verification Engineers and Managers

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