First Book Published on the Open Verification Methodology

Step-by-Step Guide Documents Best Practices for OVM World Community

SAN JOSE, Calif., and WILSONVILLE, Ore., May 29, 2008 – Cadence Design Systems, Inc. (NASDAQ: CDNS) and Mentor Graphics Corp. (NASDAQ: MENT) today announced the publication of the industry’s first book covering the widely adopted Open Verification Methodology (OVM). Step-by-Step Functional Verification with SystemVerilog and OVM is written by Dr. Sasan Iman, an industry leader in the functional verification space. Iman is a principal with SiMantis Inc. and the former director of simulation technology at Escalade Corp. whose previous books on the e verification language and low-power design methodologies have been well received by the design and verification community. The new book from Hansen Brown Publishing is being promoted by Cadence and Mentor on the OVM World Web site (www.ovmworld.org) to help the OVM community better understand and use the popular methodology.

Step-by-Step Functional Verification with SystemVerilog and OVM provides a complete guide and reference for adopting an effective functional verification methodology, learning the SystemVerilog language, and using SystemVerilog and the OVM library for building a verification environment for a realistic design example. With more than 500 pages of original technical content, none of which duplicates the documentation already available on OVM World, the book is unprecedented in both the breadth and depth of its information on advanced verification.

“Dr. Iman brings together all the essential elements to understand the use and application of the OVM,” said Dennis Brophy, director of Strategic Business Development at Mentor Graphics. “This book has everything design and verification engineers would want to know to apply the OVM to their most pressing challenges.”

“The OVM is one of the most quickly and widely adopted new solutions ever for verifying complex chips,” said Ted Vucurevich, CTO at Cadence. “This book walks the reader through the OVM as well as the SystemVerilog language constructs upon which it is built. The breadth of this book and its pragmatic approach make it an invaluable resource for both novice and experienced verification engineers.”

“This book fulfills the need for education in two critical areas: SystemVerilog verification and the OVM,” said James Baldwin, Staff Verification Engineer at Qualcomm Incorporated. “The blending of these topics in a single book provides a unique and efficient source for any verification engineer who wants to rapidly learn these leading-edge concepts and put them to use with a solid understanding.”

“There is significant industry interest in the OVM but it can be difficult figuring out how to get started,” said J.L. Gray, owner of the popular and influential Cool Verification blog (www.coolverification.com) and an Associate Principal with Verilab, Inc. “Dr. Iman's book provides a solid introduction to the OVM and includes a set of helpful examples demonstrating key concepts related to sequences, factories and configuration constructs. It's definitely a must-read for engineers building testbenches with the OVM.”

Availability
Step-by-Step Functional Verification with SystemVerilog and OVM is now available for ordering at either of the following sites:

http://www.amazon.com/Step-step-Functional-Verification-SystemVerilog/dp/0981656218

http://www.simantis.com

Open Verification Methodology
The Open Verification Methodology, based on IEEE Std. 1800™-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $850 million and employs approximately 4,200 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

Cadence is a registered trademark and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Mentor Graphics is a registered trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

For more information, please contact:
Dan Holden
Cadence Design Systems, Inc.
408-944-7457
holden@cadence.com

Carole Thurman
Mentor Graphics
503.685.4716
carole_thurman@mentor.com