Cadence and Mentor Announce Immediate Availability of the Open Verification Methodology
Award-Winning Interoperable SystemVerilog Methodology Ready for Download
SAN JOSE, Calif., and WILSONVILLE, Ore., Jan. 9, 2008 – Cadence Design Systems, Inc. (NASDAQ: CDNS) and Mentor Graphics Corp. (NASDAQ: MENT) today announced immediate availability of the Open Verification Methodology (OVM), which was recently awarded a “2007 BEST” award for EDA technology from Electronic Design Magazine. Distributed under the standard open-source Apache™ 2.0 license, the OVM source code, documentation, and use examples may be downloaded free of charge from http://www.ovmworld.org. The OVM Web site is the central point of access for the OVM source code, providing information about partners, events, seminars, training, how-to instructions and future plans.
The OVM, based on IEEE Std. 1800™-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. The OVM provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. As a joint development initiative between Mentor Graphics® and Cadence® Design Systems, the OVM is supported on multiple verification platforms ideally suited to both novice and expert verification engineers.
“Open source, plug-and-play reuse, and multi-language support are the leading requests from our verification and training customers,” said Yoshiyumi Nagano, CEO of HD Lab. “We have reviewed other methodologies in the market, but only OVM offers this combination of capabilities. We are pleased to see the first release of the OVM source code and believe this will increase the efficiency.”
The OVM includes the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments and reusable Verification IP (VIP) in SystemVerilog. The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library, and significantly shortens the time to create verification environments, easily integrate plug-and-play VIP and ensure code portability and reuse.
“As a leading supplier of silicon IP, Denali is pleased to see the significant traction OVM has gained throughout the industry,” said Juirong Cheng, vice president of engineering at Denali Software. “The OVM 1.0 achieves the fusion of open SystemVerilog and interoperability required to enable adoption across our broad customer base. The OVM source code, documentation, and examples have the quality and interoperability we need to deliver OVM-compliant VIP this year.”
“The Open Verification Methodology represents a major step forward in protecting our customers’ investment in verification flows and reusable verification IP,” said Robert Hum, vice president and general manager of Mentor Graphics Design, Verification and Test Business Unit. “After extensive customer interaction, we believe OVM will definitely accelerate the move to SystemVerilog, and provide significant competitive advantage to design and verification teams around the world.”
“We have discussed OVM with more than a thousand engineers at customer sites and have worked with more than a dozen customers and partners during the Beta period,” said Ziv Binyamini, corporate vice president, Product and Technologies Organization at Cadence Design Systems. “The level of interest in OVM is overwhelming, so we are pleased to be able to make it available to the entire industry as a critical step in delivering on the full promise of SystemVerilog.”
“Doulos is pleased to be associated with the first public release of OVM, and to have worked closely with the Cadence and Mentor teams to ensure OVM adopters have access to high-quality training aligned with this release,” said Rob Hurley, CEO of Doulos. “OVM addresses the very real market need for a standard verification methodology based on SystemVerilog, and does so in style.”
A production version of OVM is available immediately with additional functionality planned for release later in 2008. Cadence and Mentor have collaborated to ensure that the OVM runs on their simulators and enables backwards compatibility with their existing environments, Advanced Verification Methodology from Mentor Graphics, and Incisive® Plan-to-Closure Methodology (Universal Reuse Methodology module) from Cadence.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $825 million and employs approximately 4,300 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
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