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Mentor Graphics Launches Veloce Product Family Delivering Industry’s Fastest Functional Verification Platform

3-5X Productivity Boost for SoC and Embedded Systems Verification

DATE Conference - NICE, France, April 16, 2007 – Mentor Graphics Corporation (Nasdaq: MENT), today announced three new next-generation hardware-assisted verification platforms. The Veloce® Solo, Trio and Quattro products are based on a new Emulation-on-Chip architecture enabling megahertz-class verification run-time speeds without compromising debug productivity and modeling accuracy for designs up to 128 million ASIC gates. This new verification family delivers the industry’s fastest “target-less” and in-circuit emulation (ICE) capability that facilitates concurrent hardware-software validation and embedded system verification for key vertical market applications such as multimedia/graphics, computing, networking and wireless designs.

"NTT routinely pushes the technology envelope to develop highly complex video processing applications. We evaluated Mentor’s Veloce hardware-assisted solutions and selected it due to its superior technology and excellent support from the Mentor team. We were impressed with Veloce’s fast compile and MHz-class in-circuit performance coupled with the ease of adoption and use," commented Ryota Kasai, Ph.D., deputy executive director, Digital Video Business Group at NTT Electronics. "Last year we deployed Veloce to verify our next-generation video codec chips and to date we have successfully taped out one of those using the Veloce system."

The Veloce product family addresses specific verification applications and use modes:

  • The Veloce Trio series maintains Mentor’s leadership position in high-performance transaction-based acceleration as well as plug-and-play, event-accurate simulation acceleration, and extends the product’s utility into embedded system verification. The rack-mountable, multi-user Veloce Trio addresses the needs of logic and system designers for up to 16 million ASIC gates in a data center-like environment.
  • The single user Veloce Solo addresses the needs of designers developing systems up to a complexity of 16 million ASIC gates in an acceleration or in-circuit emulation mode.
  • The multi-user Veloce Quattro is architected to address the needs of design teams developing systems up to a complexity of 128 million ASIC gates in an acceleration and/or in-circuit emulation mode.

“Mentor has timed this introduction pretty well. RTL simulation is running out of steam so the demand for acceleration and emulation boxes is taking off,” stated Gary Smith, chief analyst of Gary Smith EDA. “They are also following the movement of functional verification into the ES [electronic system] level. The transaction level has become dominant for the verification side of simulation in most of the large designs.”

The Veloce platform is Mentor’s fifth-generation hardware-assisted solution, established by innovative technologies from its VStation™ and Celaro™ emulation platforms. Mentor’s Veloce solution represents convergence of a number of leading and proven hardware and software technologies – Emulation-On-Chip, Virtual Wires™ and advanced software technologies such as Testbench Xpress™ based upon the Accellera Standard Co-Emulation Modeling Interface (SCE-MI).

“Our choice of Veloce was based on overall superior co-simulation and transaction-based acceleration technologies, small physical footprint, as well as fast turnaround time and ease-of-use resulting in the higher productivity required by the research programs of the CIM-PACA Plateforme de Conception,” said Yves Leduc, Texas Instruments (TI) representative, member of the conseil d'administration of the CIM-PACA Plateforme de Conception. “The Emulation-on-Chip approach used by Mentor delivers these key ingredients. We look forward to deploying the Veloce system to meet our verification challenges.”

Powered by an industry-proven 90-nanometer silicon process and Mentor’s patented VirtualWires technology, the new Emulation-on-Chip architecture delivers a three to five times boost in run-time performance compared to previous hardware-assisted solutions from Mentor. This architecture also provides fast compile times of up to 15 million RTL equivalent gates per hour. Unlike other hardware-assisted tools based on commercially available FPGA technology, the Veloce compiler dramatically shortens the model build time.

The Veloce platform also enables simulation-like debug visibility on every signal in the design without compromising capacity or run-time speed. The faster turnaround time allows designers to execute numerous and longer tests to finish RTL and system-level validation with a higher degree of first-pass confidence.

“Our customers continue to experience increasing pressures for first-pass silicon and software success, requiring extensive chip-level and system-level functional verification within shortened project schedules. In response to these requirements, Mentor has dedicated significant resources over the past several years toward development and deployment of the new Veloce product family,” stated Eric Selosse, vice president and general manager of Mentor’s Emulation Division. “The server-like characteristics of the Veloce Trio, combined with the enterprise class Quattro and personalized Solo, deliver breakthrough price/performance and ease-of-use in a ready-to-deploy package.”

The new Veloce family further strengthens Mentor’s leadership in high-performance transaction-based acceleration. It delivers megahertz-class acceleration compliant with Accellera’s third-generation Standard Co-Emulation Modeling Interface (SCE-MI 2.0). It is architected based on the SystemVerilog Direct Programming Interface to deliver up to 1000X performance improvement over the fastest software simulator without compromising interoperability. The new transaction compiler de-couples the software simulator from the high-performance Veloce family to accomplish an optimal mix of bandwidth and communication latency.

Product Unveiling at DATE 2007
The new Veloce family will be unveiled at the DATE Conference, in Nice, France, on Tuesday, April 17 at 11:00 a.m. at the Mentor Graphics booth, M3 Mediterranée Level 1. The product will be demonstrated during the DATE Conference.

Pricing and Availability
Flexible business models are available including short-term rentals, long-term leases, and purchases. Monthly rental pricing for Veloce Trio starts at $21,000 (USD) for 8 million gate capacity. Veloce is shipping in volume production worldwide and supports the Linux platforms. Existing Mentor customers will have an option to transition to the new product families. For additional product information visit the website at www.mentor.com/med.

About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,250 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: www.mentor.com.

Mentor Graphics and Veloce are registered trademarks and VStation, Celaro, Testbench Xpress and VirtualWires are trademarks of Mentor Graphics Corporation. All other company and/or product names are the trademarks and/or registered trademarks of their respective owners.

For more information, please contact:
Larry Toda
Mentor Graphics
503.685.1164
larry_toda@mentor.com

Suzanne Graham
Mentor Graphics
503.685.7789
suzanne_graham@mentor.com

 
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