Mentor Graphics Updates VStationTBX Verification Accelerator, Delivering Full Language Support for System C
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WILSONVILLE, Ore., April 15, 2004 - Mentor Graphics Corporation today announced an updated version of its VStationTM TBX verification accelerator that delivers full support for the leading system design languages. The VStationTBX tool now accelerates test benches in System C, generating verification results more than 500 times faster than co-simulation methods, and more than 10,000 times faster than software simulation. The updated VStationTBX tool extends the Mentor Graphics® Scalable VerificationTM Platform, an interconnected suite of tools providing system-level verification and debugging for complex application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The VStationTBX tool, through its test bench compiler, compiles behavioral hardware description language (HDL) along with RTL, allowing designers to quickly map behavioral Verilog testbenches and memories into the VStationPRO emulator. This eliminates the performance bottlenecks and re-modeling effort of co-simulation, allowing design teams to save months on testbench execution and creation. In addition, the VStationTBX tool provides automated support for transaction-based modeling methods and standard verification languages such as SystemC, combining accelerated verification with the power of abstraction, and directed random testing. "The improvements we are making to the VStationTBX tool will allow customers to use hardware to speed complex system verification tests," said Eric Selosse, vice president and general manager of the Mentor Graphics Emulation Division. "Our verification acceleration products have been a key component of more than 50 successful tapeouts so far and are facilitating the migration to the widespread use of transaction-based verification and directed random testing together with acceleration, helping customers to shorten their verification cycles and get quality products to market faster." About VStationTBX Unlike traditional co-simulation which is limited in performance, the VStationTBX tool compiles 2-state behavioral Verilog, including behavioral memory models into the emulator, executing it directly. The VStationTBX tool's TestBench Compiler provides an initial 20-200x performance increase for existing verification environments. Once a customer is enjoying this initial performance boost, the VStationTBX tool enables them to incrementally migrate to higher abstraction, performance and productivity by using Mentor's third generation of transaction-based technology to smoothly connect abstract C or hardware verification language (HVL) models to their design and test bench components in the emulator.
About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $675 million and employs approximately 3,700 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com. Mentor Graphics is a registered trademark of Mentor Graphics Corp. VStationTBX and Scalable Verification are trademarks of Mentor Graphics. All other company and/or product names are the trademarks and/or registered trademarks of their respective owners. ###
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