Sign In
Forgot Password?
Sign In | | Create Account

Questa Vanguard Program - Partner Details

Vanguard Program Details

Agnisys Technology Pvt. Ltd.

Agnisys Technology Pvt. Ltd.

Company URL: http://www.agnisys.us
Country: INDIA
Contact: Anupam Bakshi
Email: anupam@agnisys.us
Phone: 978-631-0505

Company Info
Agnisys Technology Pvt. Ltd. is a micro-global company that provides focused Engineering and IT services at affordable prices. The Hardware Design and Verification services division is focused on providing expert engineering talent using the following technologies: SystemVerilog SystemC Verilog VHDL Our past work has been in the following domains: Video/Image/Audio processing Video Codecs Networking SONET

Testimonial/Quote
Our acceptance to the Questa Vanguard program has been a boon for us at Agnisys. Not only are we able to offer verification/design training and consulting services, we have also embarked on development of a new product called IDesignSpec which would generate Questa and AVM qualified outputs. Mentor's Questa Vanguard program is the fuel that powers our creative engines. We no longer have to design our products in a vacuum. We feel connected with the SystemVerilog/SystemC ecosystem right from the get go. The AVM and its SystemVerilog implementation have taken away months of wasteful, unnecessary work. These technologies enable us to create VIP that we know would work for any customer who is already using Questa. We hope that AVM is adopted as an industry standard.

Customized Verification IP capabilities
Codecs: JPEG, DNxHD (VC3) Buses: PCI-X, PCIe, USB 2.0, I2S, properiatary busses. Video: Up/down sampling, scaling, blur, image transformations and other effects algorithms. Audio: Sample rate conversion

Verification Service Portfolio
Complete concept to tape out Verification services. Creation of Verification Plan. Verification methodology and tool selection. Transactor development. Translation of Verification infrastructure to SystemVerilog or SystemC.

Verification Training Courses
Introduction to SystemVerilog Advanced SystemVerilog Introduction to SystemC Advanced SystemC

Questa Integration
1) IDesignSpec (IDS) is an engineering tool that allows a chip or system designer to create the design specification once and automatically generate all possible views from it, without re-write or any duplication. We are working to make IDS outputs compatible with Questa. Our mutual customers would benefit from the higher quality of the generated results. 2) We develop all our transactors on Questa, this enables us to make sure all our transactors work with the latest tools.
 
Online Chat