Products A to Z - Functional Verification

  • Certe Testbench Studio

    Certe Testbench Studio delivers a powerful, yet familiar, environment that enables the rapid creation and complete understanding of OVM and SystemVerilog-based testbenches for complex ASIC and FPGA designs.

  • FormalPro

    FormalPro is a high-capacity equivalence checking solution for regression testing of ASICs and ICs. FormalPro uses formal verification techniques to prove that a design is equivalent to its golden reference model.

  • HDL Designer

    HDL Designer provides engineers with a suite of advanced design editors to facilitate development: interface-based design spreadsheet editor (IBD) and block diagram, state-machine, truth table, flow chart and algorithmic state-machine editors.

  • iSolve Application Solutions

    High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs

  • ModelSim®

    ModelSim combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments.

  • Questa ADMS

    Questa ADMS is a language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal system-on-chip designs.

  • Questa Codelink

    Codelink is an advanced debug toolset for functional verification of processor-based designs using your RTL or gate-level processor models. Codelink aids processor-driven verification by dramatically improving processor visibility and reducing the time it takes to debug failing processor-driven tests. It connects to existing processor signoff models without changing the design or simulation results.

  • Questa Power Aware Simulator

    The Questa Power Aware Simulator enables design teams to verify the architecture and behavior of active power management planned for the implementation, but starting much earlier in the design process.

  • Questa Verification IP

    Using Questa Verification IP you can reduce the overall testbench development time and complete more verification with less effort.

  • Questa Verification Management

    There are three dimensions to any IC design project: the process, the tools and the data. Questa® offers a comprehensive approach to the problem with its verification management option that handles all within a scalable and modular solution.

  • Questa® Advanced Simulator

    The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF

  • Questa® CDC Verification

    The Questa Clock-Domain Crossing (CDC) Verification solution focuses on the interaction between these clock domains. Questa CDC addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques.

  • Questa® Formal Verification

    The Questa Formal Verification tool complements simulation-based RTL design verification by analyzing all possible behaviors of the design to detect any reachable error states.

  • Questa® inFact

    Questa Questa inFact targets as much functionality as traditional constrained random testing, but achieves coverage goals 10X to 100X faster.

  • ReqTracer

    Manage requirements in your FPGA and ASIC design flows. ReqTracer simplifies, automates and enables requirements traceability from hardware specification through HDL coding, implementation, verification and validation.

  • TestBench XPress

    High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs

  • Veloce

    High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs

  • Veloce Transactors

    High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs

  • Virtual Devices

    High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs

  • Vista Architect

    Vista™ Architect, a superset of the Vista Design solution, is a complete TLM 2.0-based solution for architecture design and exploration enable system architects and SoC designers to make viable architecture decisions, prototype and analyze complex systems.

  • Visual Elite

    Visual Elite™ is the state-of-the-art design and integration platform enabling designers and system architects to intuitively capture and connect SystemC, TLM 2.0 and HDL blocks into complex SoC’s and systems.