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Questa Clock-Domain Crossing (CDC) Verification

The industry’s most comprehensive and easy-to-use clock-domain crossing verification solution

Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The Questa® Clock-Domain Crossing (CDC) Verification solution focuses on the interaction between these clock domains. Questa CDC addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques.

An RTL or gate-level simulation of a design that has multiple clock domains does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process. The Questa CDC Verification solution solves this problem.

Overview

How Questa CDC Verification Works

Performing clock-domain crossing verification with Questa CDC is straightforward. The CDC compiler analyzes the RTL code, identifies all clocks and clock-domain crossings, and offers a rich, intuitive debugging environment to resolve all types of CDC issues. Once these issues are resolved, it automatically generates a set of protocol assertions and metastability models that are linked in to the simulation of the RTL code.

The Three Essential Elements of CDC Verification

The Questa CDC Verification solution sets the industry benchmark by providing the three essential elements for a complete clock-domain crossing (CDC) verification solution: structural or static CDC analysis, CDC protocol verification, and CDC reconvergence verification. Questa CDC Verification is the only solution that enables you to accurately predict the behavior of silicon. It gives you the confidence that all of your CDC bugs will be found before tapeout and expensive respins will be avoided.

Benefits

Immediate productivity: Questa CDC automatically identifies your clock and clock distribution strategy, minimizing set up time.
Testbench free: Simply read in your RTL design and Questa CDC will pinpoint all potential CDC issues.
Most accurate reporting: Fewest false negatives in the industry, so you don’t waste time chasing non-issues.
Familiar Visualization: CDC-centric analysis and debugging GUI leverages familiar schematics and waveforms where appropriate.
SoC-level design capacity: Questa CDC's high performance analysis can process 100-million-gate designs and its hierarchical capabilities enable unlimited capacity

Flexibility: Fully leverage your existing verification infrastructure and testbenches to ensure maximum productivity.
Most comprehensive debug: Patented, automated metastability injection is the only way to find complex CDC reconvergence bugs.
Verification management: Automatic coverage reporting for CDC protocol and reconvergence verification enables you to effectively manage the overall verification process.
Ease of use: Questa CDC supports Synopsys Design Constraints (SDC) format constraints for clock and port domain settings and includes a TCL scripting environment with powerful control and reporting capabilities

Datasheet

White Papers

Five Steps to Quality CDC Verification
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Multimedia

Clock-Domain Crossing Verification for FPGAs
On-demand Web Seminar

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Questa Training

We have training courses available for Questa products in our training centers around the world, online, or at your site.

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Contact Mentor Graphics

Questa® CDC Verification Info Request or call toll free: 1-800-547-3000

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An online forum to provide updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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