Questa® Clock-Domain Crossing (CDC) Verification
The industry’s most comprehensive and easy-to-use clock-domain crossing verification solution
Metastabilty from the intermixing of multiple clock signals is not modeled by simulation. Unless you leverage exhaustive, automated Clock Domain Crossing (CDC) analyses to identify and correct problem areas, you will inevitably suffer unpredictable behavior when the chip samples come back from the fab. Bottom-line: automated CDC verification solutions are mandatory for multi-clock designs.
When Good Clocks Go Bad
Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has multiple clock domains does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process.
The Solution: Questa CDC Verification
Questa CDC Solutions identify errors that have to do with clock domain crossings – signals (or groups of signals) that are generated in one clock domain and consumed in another. It does so with structural analysis and recognition of clock domains, synchronizers, and low power structures (via UPF); and with generation of metastability models for reconvergence verification. The technology checks all potential failure modes and presents to the user familiar schematic and waveform displays. Additionally, in concert with simulation this technology can be used to inject metastability into functional simulation to verify the DUT correctly processes asynchronous clocks.
- Statically verifies that all signals crossing asynchronous clock domain boundaries are guarded by CDC synchronizers
- Checks integrity of clock-domain crossing (CDC) paths in the design
- Supports an extensive set of pre-defined and user-defined CDC schemes
- Comprehensively verifies the structure, protocol and reconvergence of all schemes
- Uses Questa CDC and UPF power intent files to verify that introduction of low-power circuitry does not introduce CDC issues
- Integrated GUI debugging
- Tight integration with Questa Formal
- Integration / results reporting with IEEE standard UCBD to electronically communicate progress and success into the main verification database (via Verification Manager).
- Immediate productivity: Questa CDC automatically identifies your clock and clock distribution strategy, minimizing set up time. Simply read in your RTL design and Questa CDC will pinpoint all potential CDC issues – no testbench is required.
- Ease of use: Questa CDC supports Synopsys Design Constraints (SDC) format constraints for clock and port domain settings and includes a TCL scripting environment with powerful control and reporting capabilities
- Low Noise, High Accuracy: Fewest false negatives in the industry, so you don’t waste time chasing non-issues.
- Familiar Visualization: CDC-centric analysis and debugging GUI leverages familiar schematics and waveforms where appropriate.
- Low Power Intent Awareness: reuses your UPF file without modification to ensure low power circuitry does not introduce CDC-related issues.
- SoC-level scalability: Questa CDC's high performance analysis can process 100-million-gate designs and its hierarchical capabilities enable unlimited capacity.
- Focused integration with simulation: Patented, automated metastability injection is the only way to find complex CDC reconvergence bugs.
- Verification management: Automatic coverage reporting for CDC protocol and reconvergence verification (via UCDB) enables you to measure CDC verification progress and the quality of the testbench with respect to CDC protocols, and effectively manage the overall verification process.