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Questa® CoverCheck

Code Coverage Closure

Questa CoverCheck is an automatic formal solution for achieving code coverage closure. The tool addresses an incontrovertible fact of verification: no matter the combination of techniques used, even after running an exhaustive battery of tests, some small fraction of uncovered code always remains.

Verification engineers are left to craft directed tests to reach the uncovered code or write the waivers explaining why the code isn’t meant to be tested, if for example, it’s deemed to be an irrelevant segment of a reused block of IP. Completing both tasks, which take an inordinate amount of time if done manually, can be done relatively quickly through the use of CoverCheck.

Questa CoverCheck reads code coverage results from simulation in the Unified Coverage Database (UCDB) and then leverages AutoCheck technology to do various useful verification tasks with regards to the coverage holes. The most obvious: prove that the code can be safely ignored. That is, the tool might mathematically prove that no stimulus could ever activate the code in question. In such cases, waivers are automatically generated to refine the code coverage results. Secondly, the tool can also identify segments of code that, though difficult to reach, might someday be exercised in silicon. In such cases, CoverCheck helps point the way to testbench enhancements to better reach these parts of the design. Finally, CoverCheck flags code coverage items that are difficult to reach by formal techniques and haven’t been hit in simulation, and thus provides a valuable measure of verification complexity.

Benefits

Automates code coverage closure

Achieve 100% coverage with automatic formal reachability analysis.

Improved fidelity of code coverage results

Eliminate code that is never meant to be exercised.

‚ÄčMode sensitive analysis

Tune the code coverage reporting considering only the relevant modes of operation.

Guide testbench enhancement

Waveforms show how uncovered but formally reachable coverage bins can be hit in simulation.

 
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