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Questa® CoverCheck

Automating code coverage closure

Questa CoverCheck is an automatic formal solution for achieving code coverage closure faster. The tool addresses an incontrovertible fact of verification: no matter the combination of techniques used, and even after running an exhaustive battery of tests, some fraction of uncovered code always remains.

Code Coverage’s “Last Mile” Problem

For D&V engineers, few things in verification are more frustrating than watching the code coverage score plateau well short of your coverage spec. No matter how many clever directed test you write, no matter how many different random seeds you try, the coverage score simply flat-lines. In parallel, specifying waivers to deliberately exclude unused IP configurations from the analysis can be a tedious and error prone manual process.

Questa CoverCheck
Questa CoverCheck automatically traverses your DUT’s state spaces and identifies unreachable areas, enables the user to “waive”/exclude items from future analyses, and pipe all results into a Unified Coverage DataBase (UCDB) for inclusion in Questa Verification Manager analyses and progress reporting.

The Solution: Questa CoverCheck

Questa CoverCheck is an automatic formal solution for achieving code coverage closure. Specifically, CoverCheck reads code coverage results from simulation via UCDB and targets the coverage holes. The results include:

  • Formal proof that the code can be safely ignored. In such cases, waivers are automatically generated to refine the code coverage results.
  • Leveraging the formal engines under-the-hood to generate waveforms showing how to reach the coverage points, thus guiding the user in how to enhance their simulation testbench to cover these items.
  • Flagging of code coverage items that are difficult to reach by formal techniques and haven’t been hit in simulation; thus providing a valuable measure of verification complexity. This guides engineers to change their designs to make them more easily verifiable.


  • Exhaustively identifies dead code areas
  • Can generate a “witness trace” waveform to show how to reach a specific cover point in simulation
  • Easy to use waiver creation marks “legitimately dead” areas (due to deliberately unused IP configuration modes, etc.) for downstream tools
  • On-going coverage measurements by Questa Advanced Simulator and Questa Verification Manager will automatically exclude these areas
  • Supports all popular forms of code coverage: line/statement, branch, toggle, conditional, expression, FSM, cover groups
  • Powerful debugging environment - Easily links to related source code, schematics, waveforms and state diagrams


  • No time is wasted dreaming up tests to try to cover unreachable code
  • Automatically improves design quality – and potentially saves die area -- by exhaustively finding dead code areas

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