Questa Verification Platform

10X-100X Faster coverage closure

Questa intelligently generates stimulus to ensure that high test quantity does not come at the expense of high test quality. The result is a 10X-100X gain in verification productivity. Questa Verification Management reduces the time needed to manage regression testing and merge coverage results from hours to minutes. Questa also eases testbench programming by automatically generating coverage models.

Low-power verification

The Questa Verification Platform is a comprehensive solution for verifying power management in low power designs. Questa Power Aware Simulation (PASim) verifies the power management architecture through both static analysis and simulation. Questa ADMS integrates with Questa PASim to verify power management in designs with analog/mixed-signal functionality. Questa CDC verifies clock domain crossings inherent in designs with active power management. Questa Formal exhaustively verifies power control logic. And Questa Verification Management ensures that power management structures are thoroughly verified as part of coverage closure.

Powerful Unified Debug

Debug is one of the most important verification technologies and critical for achieving productivity in today’s complex designs. The Questa Verification Platform has unified debug that reaches across the verification engines of Questa Simulation, Questa Power Aware Simulation, Questa Formal/CDC and Veloce Emulation/TBX. It provides high performance and capacity for RTL and Gate Level design in all supported HDL languages. It also includes advanced features such as causality tracing, advanced assertion debug, FSM debug, schematic debug, SystemVerilog debug, UVM Aware Debug and transaction level debug all to improve productivity in a unified testbench and RTL/Gate environment.

Formal-Based Technologies

Questa Formal-Based Technologies offer the unique ability to root out obscure bugs and increase design confidence through exhaustive analysis. Questa offers a broad spectrum of formal solutions, ranging from fully automatic applications such as clock-domain crossing verification, code coverage closure and automatic formal checking to custom coded assertion property checking with high-powered formal engines. These solutions work as a complement to simulation-based methods and they boost verification productivity by targeting verification tasks that are otherwise difficult to complete.

Leading support for UVM

The Questa Verification Platform is the first verification platform with a UVM-aware debug solution that provides engineers essential information about the operation of their dynamic class-based testbenches in the familiar context of source code and waveform viewing.

Questa lets you see the component hierarchy, class definition tree, and other UVM settings specific to your testbench to make it easier to understand the operation of your verification environment. Together with UVM Express, UVM Connect, and Mentor’s UVM Questa Verification IP, the Questa platform provides an unmatched environment.