Questa

High Performance and Capacity Mixed HDL Simulation

Questa combines high performance and capacity with comprehensive support of SystemVerilog, VHDL, and SystemC. Questa is the most comprehensive advanced verification platform reducing the risk of validating the most complex FPGA and SoC designs.

The Questa vopt usage mode achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms of SystemVerilog and VHDL, improving SystemVerilog and mixed VHDL/SystemVerilog RTL simulation performance by up to 10X. The performance mode can also improve Verilog gate-level performance by up to 4X and capacity by over 2X. Questa also supports very fast time-to-next simulation and effective library management while maintaining high performance with its new black box use model, known as bbox. With bbox, non-changing elements can be compiled and optimized once and reused when running a modified version of the testbench. bbox delivers dramatic throughput improvements of up to 3X when running a large suite of testcases.

Assertion Based Verification

Questa delivers a comprehensive, standards-based ABV solution, offering the choice of SystemVerilog, Property Specification Language (PSL), or both. To ease the adoption of ABV, Questa also includes the Questa Verification Library (QVL). QVL is a comprehensive SystemVerilog assertion checker and monitor library that makes it easier to adopt ABV. With built-in coverage measurements, QVL integrates into any coverage-based methodology. QVL assertions can be used with any simulator and is the only assertion library optimized for formal verification and emulation.

QVL Monitors

• APB
• APB3
• AXI
• AHB
• DDR2 - SDRAM
• DDR3 – SDRAM (to be released)
• DDR-SDRAM
• Ethernet
• HDMI (in progress)
• I2C
• LPC
• OCP2.2
• PCI
• PCI Express 2.0
• SAS
• SATA
• SPI4.2
• USB1.1
• USB2.0

Test Automation

Questa verification features enable the automatic creation of complex, input-stimulus combinations that are extremely time-consuming to create manually. Stimulus scenarios can be described in terms of constraints using SystemVerilog and SystemC Verification (SCV) library constructs. These constrained-random features help promote reuse at the testbench level, thereby reducing the number of testbenches that need to be written while increasing the amount of tests generated, bugs exposed, and verification coverage achieved.

Questa combines functional coverage with constrained-random testing to identify the functionality exercised by the automatically generated stimulus. Using functional coverage metrics as feedback for test creation, engineers can adjust constraints to focus random testing on coverage holes. This automation methodology offers huge productivity improvements compared to handcrafting hundreds of directed tests. Functional coverage metrics are provided through SystemVerilog coverage models (covergroups and coverpoints) and assertion languages (either SystemVerilog or PSL assertions and cover directives). Questa collects all coverage data — code coverage, assertions, formal, and functional coverage — into a single highly efficient Unified Coverage DataBase (UCDB) and makes them available in real-time within the testbench or for post-processing with Questa Verification Management.

Quest Verification Management

The application of constrained-random test stimulus and metrics-driven verification dramatically increases the amount of data generated in the verification process. Questa Verification Management analyzes coverage and verification data, providing up-to-date information on the status of verification test suites and insight into how to improve the efficiency and effectiveness of the verification process.

Questa Verification Management imports verification test plans and correlates coverage results to test plan objectives, delivering a powerful tool for managers and engineers to continuously track progress and efficiently deploy resources against plan, providing a level of process visibility and efficiency formerly unavailable. Questa Verification Management provides powerful analysis utilities that enable verification managers to easily identify when specific areas of the plan are on-target or not. By associating priorities and weightings with plan objectives, the relative impacts of being on or behind schedule can inform difficult choices over the course of a project.

Integrated Multi-Language Debugging

The Questa debug environment fully supports all standard languages, and its GUI usage model is consistent across all languages and abstraction levels. Questa automatically recognizes key objects in the design and verification environment, providing intuitive ways to view and debug these objects. For example, finite state machines (FSM) are inferred, and an FSM debug window provides a natural way to visualize the current state and state transitions of the FSM over time. Verification environments that are constructed with the OVM class library are recognized as part of the overall simulation hierarchy, even though the components of the verification environment are dynamic class objects. Questa manages the hierarchy automatically. Questa helps automate the often time-consuming and tedious process of tracing causality from an observed error to the root cause of the bug. Through either a graphical or source based dataflow, the source and sink (driver and reader) relationships can be easily traversed to identify the origin of a bug.

Low Power Verification

The management of power consumption is critical for many applications. The techniques required to manage power present unique design and verification challenges. Questa’s Power Aware Simulation (PASim), combined with Accellera’s Unified Power Format (UPF) standard, mitigates the risks of implementing low power silicon designs by accurately modeling low power silicon behavior early in the design cycle.

PASim understands how the power network is constructed and connected to the design logic. It applies corruption (power-down) behavior when the supply to a power domain is shut-down, corrupt-on-activity behavior when a power domain is in a non-operational bias mode, isolation logic functionality for ports on power domains, and retention capabilities to registers as defined by the UPF specification. Questa’s PASim provides the industry’s only capability to accurately model retention register behavior. The relationships of save and restore retention functionality, relative to other operational register controls such as reset and clock, differ widely from one technology library to another, even across technology nodes for the same silicon foundry. Verification of a low power design’s power down and up sequence is incomplete or incorrect if generic retention register behavior is used. PASim supports behavioral descriptions of retention register functionality, ensuring that simulation results match hardware behavior. With PASim, simulation results ensure that the design’s low power management techniques are designed and implemented correctly for the targeted implementation technology