Binding SystemVerilog to VHDL Components Using Questa SystemVerilog offers a rich set of testbench automation capabilities, native assertions, and functional coverage. These features make SystemVerilog increasingly appealing to VHDL users who need to implement an efficient and effective functional verification methodology.

The Questa(tm) advanced verification environment offers native support of SystemVerilog, Verilog, and VHDL, making it easy to adopt SystemVerilog.

The flexibility provided by Questa's single kernel architecture enables VHDL users to easily attach SystemVerilog to existing VHDL components. The connection is made using the SystemVerilog bind function, which gives modules and program blocks access to both external ports and internal signals in the bound VHDL object. Among other things, you can use this capability to monitor VHDL functionality with SystemVerilog Assertions (SVA) or assess the functional coverage of VHDL designs.