The expressive power of SystemVerilog assertions (SVA) with local variables enables you to specify complex properties in a concise form (for example, properties involving data integrity). However, using local variables might result in unacceptable performance during simulation or formal verification if you do not take precautions when coding your assertions.

This paper provides a set of coding guidelines and a methodology for efficient SVAlocal variable use. Our guidelines allow you to take advantage of the expressiveness of SVAlocal variables while avoiding potential pitfalls that can result in reduced performance and capacity.