Power consumption due to leakage has become a major factor in the total power consumption equation for battery powered and sub-100 nm designs, compelling design teams to adopt various power management design techniques. Power gating is one of the most effective techniques for managing leakage power.

In addition, at sub-65 nm process nodes, different biasing techniques are being combined with power gating in order to minimize leakage power. Employing low power techniques, such as power gating and substrate biasing, gives rise to many thorny verification challenges. For example, are the power control sequences correct; is my biasing strategy functionally correct; do the “awake” portions of the design still function correctly when other domains are powered down; is adequate state information retained when state retention is employed; is the proper retention protocol followed; and is my isolation strategy functionally correct.