When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. These less-than-stellar outcomes seem to be happening more and more often. Firsttime success with silicon is waning, down from nearly 40% in 2002 to less than 30% in 2007, according to an independent verification survey funded by Mentor Graphics.

Re-spins are mainly due to functional or logical flaws in the design, which suggests an increasing number of problems in the overall verification management process. Among such problems: a dearth of tools that can allow the specification to drive the process and can manage the volumes of data generated during verification. What’s needed is a common platform and environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project. And not just to the verification plan, but also to the specifications and the design, both of which tend to change through time.

There are three dimensions to any IC design project: the process, the tools and the data. Any comprehensive approach to verification management needs to handle them all.