Accelerated Verification of a MATLAB-Driven Digital FIR Filter RTL Design Using Veloce and TBX

ABSTRACT

This paper explores the verification of DSP and communication system Systems-on-Chip (SoC’s) using a typical signal processing system subsystem - in this case a very large parallel digital FIR filter - using MATLABTM from The MathWorks in an interoperable manner with a very high performance emulation system. The results are presented here using Mentor Graphics’ Veloce emulator and its TestBench Xpress (TBX) SceMi2.0 compliant transaction-based hardware acceleration application. The complete verification system architecture consists of a testbench comprised primarily of MATLAB calls made from a SystemC main program to an "engine" provided by The MathWorks. This engine is a separate process created at system initialization time by the SystemC program, and all but the design DUT and three transactors run on the Veloce host computer. Data is sourced and retrieved to and from the engine via calls made available in the engine's API. The data is created, processed, and displayed via string passing calls made from the SystemC to the engine. These strings are identical to MATLAB commands that are expected in the normal MATLAB console application. The signal stimulus provided by the testbench/MATLAB sub-system is delivered to the DUT via SystemVerilog DPI transactors running within TBX. Likewise, response vectors from the DUT are returned via another transactor to the testbench and the MATLAB engine for post-processing and display.