Addressing Today's Complex Clock Modeling Issues with Veloce Emulation Technology

ABSTRACT

Earlier designs were smaller, less complex, and had simpler clocking. A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use of System-on-Chip (SoC), designs today are becoming extremely complex with an increasing number of peripherals/external interfaces to consider, requiring a higher numbers of asynchronous clocks.

The large numbers of asynchronous clocks are driven by the increased number of different peripheral interfaces in the SoC. Typically, peripherals have their own distinct clock that is asynchronous to other clocks which means designers don?t have much control over peripheral clocks.

SoCs serve many different purposes. A flexible chip that can be used in multiple applications has more interfaces than a single-purpose chip. Asynchronous clocks allow designers to reuse peripheral IP as well as implement power save states, but doing this brings additional verification challenges for design and verification houses. Designers can rely on the best practice techniques and software tools for synchronous designs or designs with at the most two asynchronous clocks. Emulation becomes essential if the complexity increases beyond two clock domains.

This white paper highlights the different types of emulators and brings to light various situations to help users select the appropriate verification tools.