This paper presents essential components of an equivalence validation environment and commonly used methods to apply it effectively.To achieve good verification coverage on mixed signal SoCs, abstract models of analog components are used. These abstract behavioral models capture functional features of analog behavior in digital HDL and are orders of magnitude faster than simulating SPICE. To effectively use the behavioral models in SoC level verification it is important to establish the equivalence between the model and implementation (SPICE).
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AMS, analog abstraction, Analog Design, analog verification, Assertion-Based Verification, Assertions, Coverage, event-driven model, IP, Questa ADMS, Questa® ADMS, real number model, SPICE