With the number of clock domains increasing in today's complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verification. After having a CDC test plan, an effective CDC verification methodology should include structural, protocol, and metastability verification. This ensures that CDC signals are handled reliably at the design stage, avoiding costly respins after they are fabricated. We will outline how these are applied to block-level and top-level RTL modules. We will describe a few common CDC violations and the techniques used to determine whether they are real design issues or not. Finally, we will summarize and highlight the results of applying this methodology to a few designs.