Five Steps to Quality CDC Verification
White Paper
ABSTRACT
With the number of clock domains increasing in today's complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verification. After having a CDC test plan, an effective CDC verification methodology should include structural, protocol, and metastability verification. This ensures that CDC signals are handled reliably at the design stage, avoiding costly respins after they are fabricated. We will outline how these are applied to block-level and top-level RTL modules. We will describe a few common CDC violations and the techniques used to determine whether they are real design issues or not. Finally, we will summarize and highlight the results of applying this methodology to a few designs.
Related Resources
Automating Software-Driven Hardware Verification...
On-demand Web Seminar 39:01Automating Software-Driven Hardware Verification with Questa inFact
Today’s complex designs increasingly include at least one, and often more, embedded processors. Given software’s increasing role in the overall design functionality, it has become increasingly...
TAGS: Functional Verification, iSDV, SoC, Verification, Questa inFact
FPGA Verification with Assertions: Why Bother? A...
White PaperFPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions
This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting...
TAGS: Avionics, COTS, SWaP, Thermal Characterization, Thermal Simulation, Questa Advanced Simulator
Advanced UVM Debugging
On-demand Web Seminar 47:58Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.
TAGS: Debugging, UVM, Questa Clock-Domain Crossing (CDC) Verification, Questa Formal Verification , Questa Codelink, Questa inFact, Questa Advanced Simulator, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification Management, Questa Verification IP

