Improving Efficiency, Productivity, and Coverage Using SystemVerilog OVM Registers

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ABSTRACT

A subset of the currently used solutions will be described in this paper, followed by a list of register verification requirements, a description of some register testing styles and modes, along with a review of coverage modes and coverage goals and finally a short overview of such tools in use and the issues identified. The SystemVerilog [1] OVM [2] Register Package will be used to illustrate various techniques for verification and its API described listed in the appendix.

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